1. Field of the Invention
The present invention relates to a semiconductor device and a method for recovering the same, and more particularly to a redundancy technique.
2. Description of the Related Art
In recent years, a redundancy technique is widely used in semiconductor devices, such as semiconductor memory devices in particular, in order to improve the manufacturing yield. The redundancy technique means a technique of adding redundant elements to prime elements (e.g., word lines, column lines or I/O lines). If one of the prime elements has a defect, the defective element is replaced with a redundant element, so that the defect can be remedied. The term xe2x80x9credundancyxe2x80x9d originally means duplication or repetition of elements. However, as the technique for replacing a defective portion with a redundant line (or a redundant memory cell) is generalized, the replacement itself has come to be called xe2x80x9credundancy techniquexe2x80x9d. Therefore, in this specification, the term xe2x80x9credundancyxe2x80x9d means xe2x80x9crecovery of the semiconductor device including a defective portion by use of a redundant line or redundant memory cellxe2x80x9d.
The conventional redundancy technique will be described with reference to FIGS. 1A and 1B. FIGS. 1A and 1B are schematic diagrams showing a word line redundancy system in a conventional DRAM (Dynamic Random Access Memory). FIG. 1A shows a case in which the word line has no defect, while FIG. 1B shows a case in which the word line has a defect.
When a row address and a word line select command are input to a row control circuit 100 from outside, a redundancy control circuit 200 compares the input row address with redundancy information. The redundancy information means the address of a defective word line. The redundancy information is stored in a fuse, a latch or the like during a memory test time. Access to the memory is performed so as to avoid a defective portion by virtue of the redundancy information.
If the redundancy information does not match with the row address, the redundancy control circuit 200 determines that replacement of the word line is unnecessary. Accordingly, a row decoder 300 selects a word line for normal access (prime word line) (see FIG. 1A). If the redundancy information matches with the row address, the redundancy control circuit 200 determines that replacement of the word line is necessary. Accordingly, the row decoder 300 selects a redundant word line in place of the prime word line (see FIG. 1B).
FIG. 2 is a block diagram of the redundancy control circuit 200 and the row decoder 300.
The row decoder 300 has prime word line drivers 310 for the respective prime word lines, and redundant word line drivers 320 for the respective redundant word lines. Each of the prime word line drivers 310 activates the corresponding prime word line, and each of the redundant word line drivers 320 activates the corresponding redundant word line.
The redundancy control circuit 200 has redundancy information storing circuits 210 and a NOR gate 220. Each of the storing circuits 210 is connected to the corresponding redundant word line and stores redundancy information. In the example shown in FIG. 2, the respective storing circuits 210 replace the prime word line 5 with the redundant word line 0, the prime word line 26 with the redundant word line 1, the prime word line 116 with the redundant word line 2, and the prime word line 473 with the redundant word line 3. Assume that, for example, the row address xe2x80x9c5xe2x80x9d is input. The row address is compared to all redundancy information. In the example shown in FIG. 2, the row address xe2x80x9c5xe2x80x9d matches with the redundancy information xe2x80x9c5xe2x80x9d corresponding to the redundant word line 0. In this case, the output of the redundancy match line corresponding to the redundant word line 0 is set to xe2x80x9cHxe2x80x9d level. As a result, the redundant word line driver 320 activates the redundant word line 0. The NOR gate 220 carries out the logical OR among the outputs of all redundancy match lines. The result of the logical OR operation is input to the prime word line drivers 310 through a prime word line non-select line NSL. In the example shown in FIG. 2, if the output of any redundancy match line is at xe2x80x9cHxe2x80x9d level, the prime word line non-select line NSL is set to xe2x80x9cLxe2x80x9d level. In this case, the prime word line drivers 310 do not activate the prime word lines. Therefore, only the cells connected to the redundant word lines can be accessed.
FIG. 3 is a circuit diagram showing a structure of the redundancy information storing circuit 210. Although FIG. 3 shows details of only the circuit corresponding to the redundant word line 0, all of the circuits corresponding to the other redundant word lines have the same structure.
The redundancy information is held in a node al of a latch 211 in every bit. For example, in the case of a 9-bit row address, each of bits RA0 to RA8 is compared to the bit of the redundancy information held in each latch 211 by a comparing circuit 212. If the row address matches with the redundancy information, the comparing circuit 212 outputs an xe2x80x9cHxe2x80x9d level signal. Information held in a latch 213 determines whether to use the redundancy information held in the redundancy information storing circuit 210. For example, if the node b1 of the latch is at the xe2x80x9cHxe2x80x9d level, the redundancy information is used. The latch outputs an xe2x80x9cHxe2x80x9d level signal. An AND gate 214 carries out the logical AND among the outputs of the comparing circuits 212 and the output of the latch 213. The result of the logical AND operation is output to the redundancy match line. Thus, if all bits of the row address match with all bits of the redundancy information and the latch 213 holds the xe2x80x9cHxe2x80x9d level, the xe2x80x9cHxe2x80x9d level signal appears in the redundancy match line. Then, the redundant word line corresponding to the redundancy match line is selected. In this case, the output of the NOR gate 220 is at xe2x80x9cLxe2x80x9d level. Accordingly, the prime word line is in the non-select state as described above.
The conventional structure described above has the following problem: that is, even if a redundant word line is substituted for a prime word line, if the redundant word line has a defect, it is very difficult to recover the redundant word line. FIG. 4 shows this state.
In the example shown in FIG. 4, a redundant word line r0 is substituted for a prime word line p5 having a defect. However, the redundant word line r0 also has a defect. Since it is very difficult to recover the redundant word line r0, the chip including these lines is determined to be defective.
In the case described above, it is necessary to substitute another redundant word line for the defective redundant word line. This technique is disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 5-54692, paragraphs [0013]-[0017], etc. FIGS. 5A and 5B are schematic diagrams of a redundancy system according to a first embodiment the invention disclosed in Jpn. Pat. Appln. KOKAI Publication No. 5-54692. According to this system, each of resubstitution circuits 405a and 405b must have two fuses in order to re-substitute a redundant word line. Therefore, the system has the drawback that the chip has a large area.
Further, Jpn. Pat. Appln. KOKAI Publication No. 5-54692, paragraphs [0018]-[0022], describes a second embodiment, in which no fuse for re-substitution is used. FIG. 6A is a schematic diagram of a redundancy system according to the second embodiment described in Jpn. Pat. Appln. KOKAI Publication No. 5-54692.
According to this system, a spare select line decoder receives an input signal/SDE from an adjacent spare select line decoder. It does not operate if the input signal/SDE is at xe2x80x9cHxe2x80x9d level. Therefore, selection of both spare select lines L5 and L6 can be prevented. In this system, the signal/SDE is always input to the adjacent spare select line decoder. The substitution is carried out as shown in FIG. 6B. First, when xe2x80x9conexe2x80x9d defect is found in a test, the test is interrupted. Then, the spare select line L5 is substituted for the defective memory cell. Subsequently, the spare select line L5 is tested. If no defect is found, the test is restarted from the interrupted point. If there is a defect in the spare select line L5, the spare select line L6 is substituted for the spare select line 5. Thereafter, the spare select line L6 is tested. If a defect is found, the chip is determined to be a defective chip. On the other hand, if there is no defect in the spare select line L6, the test is restarted from the portion interrupted first. If there is no defect in the overall chip, the chip is determined to be a conforming chip.
However, the above system has the following problem. FIG. 6C shows a structure having three spare select lines. An input signal/SDE5 is a control signal for a spare select line decoder 408a connected to the spare select line L5. When the input signal/SDE5 is xe2x80x9cLxe2x80x9d, the spare select line decoder 408a sets the spare select line L5 to the non-select state. An input signal/SDE6 is a control signal for a spare select line decoder 408b connected to the spare select line L6. When the input signal/SDE6 is xe2x80x9cLxe2x80x9d, the spare select line decoder 408b sets the spare select line L6 to the non-select state.
FIG. 6D shows steps of testing the structure shown in FIG. 6C. It is assumed that two test steps are performed and a defective memory cell is replaced in each test step. In the example shown in FIG. 6D, two defects are found in the first test. The defective memory cells are replaced by spare select lines L5 and L6. Thus, the first test is completed.
Then, all cells are tested again. It is assumed that further defects are found in this step. In the example shown in FIG. 6D, defects occur in two types of portions: one in a prime cell, and the other in the spare select line L5. In the former case, the spare select line L7 is substituted for the prime cell, so that the defect can be remedied. In the latter case, the spare select line L7 can be substituted for the spare select line L5; however, there is no means for stopping selection of the spare select line L5. Therefore, in the case where the spare select line L7 is substituted for the spare select line L5, it is difficult to prevent multi-selection of cells. More specifically, if a cell corresponding to the spare select line L5 is to be accessed, only the spare select line L7 should be accessed in theory. In practice, however, according to the conventional structure, not only the spare select line L7 but also the spare select line L5, which includes a defect, is accessed.
A semiconductor device according to an aspect of the present invention comprises:
a prime memory cell array including prime memory cells arranged in a matrix;
a redundant memory cell array including redundant memory cells arranged in a matrix;
a holding circuit which holds an address of a defective memory cell included in the prime memory cell array;
a group of access lines respectively connected to the redundant memory cells;
a first controlling circuit which supplies a substitution command to substitute a redundant memory cell for the defective memory cell corresponding to the address held in the holding circuit, through the group of access lines to the defective memory cell; and
a second controlling circuit which, when a plurality of portions of the holding circuit hold the address of the defective memory cell, disables all but one of the plurality of portions which hold the address of the defective memory cell.
A method for recovering a semiconductor device according to an aspect of the present invention comprises:
carrying out a first test with respect to prime memory cells included in a prime memory cell array to detect a first defective memory cell;
substituting a first redundant memory cell included in a first redundant memory cell group of a redundant memory cell array for the first defective memory cell detected in the first test;
carrying out a second test with respect to all prime memory cells included in the prime memory cell array except the first defective memory cell and the first redundant memory cell substituted for the first defective memory cell to detect a second defective memory cell;
substituting a second redundant memory cell included in a second redundant memory cell group of the redundant memory cell array for the second defective memory cell detected in the second test; and
inhibiting access to the first defective memory cell and the first redundant memory cell, when the second defective memory cell is the first redundant memory cell substituted for the first defective memory cell.